1. Field of the Invention
This invention relates to integrated circuit (IC) devices and more particularly to coupling to or including on the device an indicator of the device's operational range for use in the power management of systems utilizing the device.
2. Description of the Related Art
Power consumption and associated performance and thermal issues are considerations for every computer system design. For example, a conventional notebook computer (also commonly referred to as a laptop or portable computer) has power and thermal constraints that cause it to operate at performance states below an equivalent desktop computer. Additionally, as servers become larger and utilize more power, servers must manage heat dissipation.
Many power saving techniques have been introduced to alleviate the impact of thermal and battery power constraints in systems. The frequency of operation (clock frequency) and operating voltage of a processor in a computer system determines the power consumption of the processor. Because power consumption and therefore heat generation are roughly proportional to the processor's frequency of operation, scaling down the processor's frequency has been a common method of staying within appropriate power limitations. Processors utilized in mobile applications, i.e., those used in battery powered systems, are particularly sensitive to power considerations and therefore generally require the lowest supply voltage that can achieve the rated clock speed. That is in part due to the small, densely packed system construction that limits the ability of the mobile computer system to safely dissipate the heat generated by computer operation.
Appropriately monitoring and controlling the processor's operating parameters is important to optimizing performance and battery life and/or reducing thermal power dissipated. Power management techniques can utilize operating range information to vary a processor's voltage and frequency to achieve optimum results. For example, when switching a processor's operating frequency from a higher to a lower frequency, the voltage can also be switched to the lowest supply voltage that can achieve the lower frequency. Operating range information is typically supplied by the processor's manufacturer and included in BIOS for use by power management software.
During production of a processor, the manufacturer operates the processor at a matrix of voltages and frequencies to determine the operating range for which the processor operates properly. The result of this process is a “Schmoo Plot” (also referred to as a “Shmoo Plot”) which is a graph of voltage and frequency of the operational range of the processor. There is typically a different Schmoo Plot for each process technology that a processor is implemented in, and additionally for each speed grade within that process technology. A Schmoo Plot can be converted into a performance state table (PST) containing a plurality of voltage/frequency pairs. Power management software can utilize these voltage/frequency pairs to control the voltage and frequency of the processor according to performance power states of the system. The PST can be stored, for example, in a computer system BIOS for use by a power management driver. An exemplary PST is shown in FIG. 1. A PST can include one or more Table Identification fields. The value of these fields can be a numerical value, a processor identification value or other such identifying value. A PST also includes a plurality of operational set points, for example, a set of voltage/frequency pairs within the operational range of the corresponding processor. Power management software can implement performance power states by assigning several of the set points to several performance power states. During each of the performance power states, voltage and frequency of the processor is applied according to the assigned set points.
The use of PSTs is problematic because the power management driver must be able to accurately identify the appropriate PST for a given processor. Because BIOS typically supports multiple processors, there is generally more than one PST in BIOS and the power management software has to match the appropriate table to the processor implemented in the system. The power management software typically reads the CPUID field, which includes the processor model, silicon revision and stepping number. However, the CPUID field is not an accurate indicator of which PST to use because the CPUID field typically only identifies the silicon design and not the process technology or speed grade. To determine the appropriate PST to use, the power management software must read other system related factors. For example, the software must read system information such as the front side bus (FSB) speed information and processor specific information such as start voltage and maximum frequency information. Processor specific information is typically added to the device after speed grade determination utilizing, for example, on-package laser cut elements. While the system provides the ability to read many of the laser cut elements and other registers that help to identify the processor, the information is located in many different registers, and typically in different register spaces, for example, in model specific registers (MSRs) and in I/O locations. To accurately identify a processor implemented in a system, software must read multiple locations to identify the appropriate PST to use in power management performance states.
In additional to the problem of properly identifying the processor to determine the appropriate PST to use, the addition of new processor features or new processor versions causes a need for a BIOS revision to update the PST entries or appropriate code. For example, when new features are added to a processor, the new MSRs that hold status bits for these new features are not interpreted by existing software. The processor can be improperly identified as another processor which can produce improper frequencies and voltages being applied to the processor. To take advantage of new process improvements, new entries must be added to the set of PSTs stored in BIOS. Revising BIOS code is typically a costly and undesirable solution due to cycle time, the need for verification, and an unwillingness of BIOS vendors to modify code.
It would be desirable to provide a better way to accurately identify the implemented processor and its operational range information for use by power management software.